You can learn quite a bit just using a simulator with no actual dev board, and this will give you a better idea of which one seems more suitable.Cool idea for a project. Stratix 10 SX650 series from Altera (Intel). Xilinx vs. Altera.
ZU11EG from Xilinx. (You may also find that Bing is actually better at digging up Xilinx lore than Google is, for whatever reason. Maybe the free version of Vivado is less restrictive than Quartus II.The one I like best is the one I'm not currently working on.AFAIK chipscope is free to use. Well, that's a very good question. The release follows hot on the heels of FPGA rival Xilinx, ... 30th June 2020. This structure makes clock routing difficult across banks, SLR etc.If the design is for video protocol implementation, fixed data manipulation I would prefer Xilinx devices with their advanced routing network which provides easy timing closure on your device and a better concept to market time.The UltraScale architecture CLBs consist of the following elementsBoth vendors provide excellent support with a large community base to help you out regarding any problems you may face during the design.Onboard RAM available in both devices are :-A direct comparison is not possible for the multipliers available in both devices as the structure of multipliers are different for both architectures, but the comparable DSP slice numbers with Intel multipliers coupled with the floating point multiplication support on altera devices makes Altera the clear winner in multiplier capability.Quartus prime uses the ModelSim while Vivado uses Isim as their default simulators.Logic Elements available in both devices are :-https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdfReference :- ug574-ultrascale-clb.pdfThe MMCM is the primary block for frequency synthesis for a wide range of frequencies, and serves as a jitter filter for either external or internal clocks(Electronic design, FPGA design, Embedded SW services, PCB design, Turnkey)The entire structure of each CLB is depicted below:For further information regarding the devices please use the following links :The document is divided into the following subsections with numerous subsections which dive deeper into each topic:Clocking Altera devices makes use of programmable clock tree synthesis rather than the direct approach followed by XIlinx.The PS section of both these FPGAs use the same 64 bit ARM A53 processor, with both devices boasting similar peripheral connections.The PLL’s primary purpose is to provide clocking to the PHY I/Os, but can also be used for clocking other resources in the device in a limited fashionArithmetic functions such as adders for upto 1024 bits can be performed in a single clock using the dedicated arithmetic routing.This novel clocking structure enables Altera designs to be built faster than it’s Xilinx counterparts.As a personal opinion the choice of device should be based on your end product requirement, for 5G, RF or image processing based system it is better to use Altera chips which can make use of the large array of RF & 5G IP’s as well as the floating point arithmetic to make your life as a designer easy.Altera :- https://www.intel.com/content/www/us/en/programmable/documentation/jzw1474049428757.html#joc1431448697339Each CMT contains 1 MMCM (capable of producing 4 phase synchronized clocks) andThis technique uses dedicated clock tree routing and switching circuits.Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock.This article provides a comprehensive comparison between the high-performance FPGA family of both Xilinx and Intel and will help you chose your next FPGA chip wisely.2 PLL’s each capable of producing 2 phase synchronized generated clocks, thus each CMT can accept upto 3 external clock and generate upto 8 generated clocks.The CLB / ALM structure in Altera’s devices are more complicated than what Xilinx devices have to offer.
The real problem, I think, hobbyist face with Xilinx and Altera is dealing with IP and the tool costs that are in addition to the development kit hardware. The FPGAs them selves are really similar, but you get logic analyzer in Altera's free IDE.
Unfortunately, in marketing products, as well as in politics, attacks must be responded to – if there is any bit of truth in them whatsoever. Also, one big one, Vivado's chipscope is way more intuitive to use than Altera's version. i.e LUT, RAM, MULTS, Clocking Structures.In Xilinx devices, the clock is managed using the Clock Management Tile which is placed in PHY next to each IO bank. At this point there's no religious reason to prefer either brand X or brand A.If you (meaning the OP) are a lone-gunslinger type who prefers to learn by Googling, you'll find that it's easier to Google for help with Xilinx questions. Edit: I have a DE0-Nano Altera Cyclone IV board.I've seen more/better educational support for Xilinx. This means no spartan-6 (seven series or newer parts).If you do go with Xilinx I recommend using an FPGA that is supported by Vivado (rather than their older ISE tools).Error & warning messages from Altera IDE are less cryptic than those of Xilinx,Picked up a DECA Dev board from arrow to play around with trying to write some kind of synth and learning. I think they've put more effort into high level synthesis stuff than Altera but I don't know how much that matters for what you're trying to do.Really it doesn't matter much, prob best to go with the one that has a dev kit that matches your needs.Yes, having used both the ISE and Vivado, it is a night and day difference, and that's not even mentioning how much better the Series 7 and later chips are in comparison to older FPGAs. Regarding your recent benchmark article, the article weighs heavily for Altera's FPGAs vs. Xilinx's, but then it was written by Altera. If you use Xillinx, you either have to do without it or pay for it.I'm looking to try a similar project. I use Vivado at work, and it's just a more modern and polished interface.
I have been told that very high sample rate PM is beneficial because of the constant re-scaling of the waveforms on the time axis.Do you know if any of these techniques require floating point representation of the audio waveforms? It's based off the altera max10 but over all good price for a little Dev board...Just gotta find the time now heheDo you know which companies offer free versions of thier software that are actually useable, not just demo versions? I found the Xilinx tutorials easier to get started with, but ymmv.
Chipzilla realized the importance of FPGAs early on, forecasting that a third of cloud service providers will be deploying these chips in data centers by 2020. Overall it does not matter much, most important bit is RTFM of all relevant bits as per usual.My vote is for altera, they have a lot of educational materials and I like the tools better.
(Not even sure if Altera offers it for free).
I wasn't aware that Altera's logic analyzer was free as well though.Xilinx seems to be the most common in hobby oriented boards. It's been 10 years since I touched an FPGA in school.
What does Xilinx have to say in defense? I'm pretty sure the free nios II core is more capable than the equivalent offering from xilinx. Even though similar Xilinx devices perform … Stay away from ISE. Sampling and delay typically require DDR but arent that hard. Just try comparing an Artix 7 with Vivado to a Spartan 3 with ISE.I prefer Quartus II to ISE, but I prefer Vivado to Quartus Prime (and therefore Quartus II as well).
Do you have a good source of examples and guides for something like that?