AMD’s Zen 2 architecture has been an incredible success for the company and is taking the desktop world by storm thanks to the ryzen 3000 series CPUs, and the server market is also facing serious disruption thanks to AMD increasing the core count to 64 cores with its Milan range of processors, while also improving performance across the board.In the past, AMD confirmed that Zen 3, Zen 4 and even Zen 5 are in the works, with the next-generation server chips from the company (the successor to Milan), known as Genoa.
So till now, Zen and Zen 2 had two core complexes on the same die with each CCX consisting of 4 cores.
Interestingly, this is about the same IPC bump in Zen 2 which sounds great but is a little less than what we had initially hoped for or at least what AMD's Senior representatives had hinted in interviews. "Other rumors have pointed out to a 50% increase in overall floating-point performance. It is also stated that the 3rd Gen EPYC Milan A0 silicon is currently being tested. Zen 4 and Genoa will not support older boards, and that will, of course, extend to the desktop too.If I had to speculate – with DDR5 memory, we could see more CPU cores. Just like you can’t build say an RX 5700 XT with 128-bit 7gbps memory without the constrained performance of the GPU cores because of lack of bandwidth, you can’t just keep putting more CPU cores onto a die without expanding the amount of bandwidth too.It’ll be very interesting to see what type of performance jump we can expect with Zen and Zen 4 based products, given Intel will be racing to catch up with their future CPU cores such as Sunny Cove. That came in as a surprise and wonder if Zen 2+ will finally be 8-core CCX for another leap in performance.
However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture. We also see the same number of cores too, 64 Cores / 2x. It is a chip that has been completely revamped from the group up and focuses on When asked about what kind of performance gain Milan's CPU core microarchitecture, which is known as Zen 3, will deliver relative to the Zen 2 microarchitecture that Rome relies on in terms of instructions processed per CPU clock cycle (IPC), Norrod observed that -- unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs -- Zen 3 will be based on a completely new architecture.Norrod did qualify his remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade -- AMD has said it's about 15% on average -- since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. Diving further into the core structure of the Zen 3 CCD/CCX, since the CCD has moved to just one CCX, the entire L3 cache can now be shared across all 8 cores rather than each CCX consisting of two slices of L3 caches per CCX in the previous Zen cores. At the time, the 8-core "Zeppelin" die featured two CCX with four cores, each. In theory, the impact on latency should be pretty profound and should help CPUs with lower core counts too. AMD's Zen 3 core architecture will soon be powering the next-generation While we had previously learned that AMD's Zen 3 CPU architecture was going to be a significant uplift in terms of performance and efficiency, Adored TV is saying otherwise. But with Zen 3, each CCX would hold 8 cores so that's essentially a single CCD.
It was Charlie over at SemiAccurate who’d originally said that there are more dies on Milan (he believed up to 15), but this is probably not true… unless they’re something not CPU related, such as GPU cores or HBM2 (this isn’t a piece of info I heard, to be clear… I’m just providing a way to balance his usually good info with this official confirmation).Another huge thing we can see is a shot of the CCX and CPU layout compared to that of Rome, and the differences in the Level 3 cache between a Zen 2 CCX and Zen 3 CCX are palpable. With "Zen 2," AMD reduced the CPU chiplet to only containing CPU cores, L3 cache, and an Infinity Fabric interface, talking to an I/O controller die elsewhere on the processor package.